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| Home > Embedded OEM > DRAM > DDR |
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| DRAM DDR |
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DDR has provided an evolutionary path from Synchronous DRAM (or SDR). It is the first DRAM technology to transfer data on both the rising and falling edge of the clock. JEDEC standardized DDR technology with a power supply voltage of 2.5V for transfer data rates from 266mb/s to 333Mb/s and 2.6V for 400Mb/s. DDR has been widely adopted and remains designed in a variety of applications especially for ones with longer life cycles and upgrade requirements like Servers and Networking systems. |
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| DDR - 184-Pin DIMM - Registered ECC |
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| Standard Profile (1.2”) with Nominal Voltage (2.5V) |
| Density |
Part Number |
Rank |
DIMM
Config |
Component
Config |
Voltage |
| 512MB |
WD1RE512X809-xxxx-yyz |
1 Rank |
64x72 |
64Mx8 |
2.5V |
| WD1RE512X818-xxxx-yyz |
2 Rank |
64x72 |
32Mx8 |
2.5V |
| 1GB |
WD1RE01GX818-xxxx-yyz |
2 Rank |
128x72 |
64Mx8 |
2.5V |
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| Standard Profile (0.72”) with Nominal Voltage (2.5V) |
| Density |
Part Number |
Rank |
DIMM
Config |
Component
Config |
Voltage |
| 512MB |
WD1RE512X818V-xxxx-yyz |
2 Rank |
64x72 |
32Mx8 |
2.5V |
| 1GB |
WD1RE01GX818V-xxxx-yyz |
2 Rank |
128x72 |
64Mx8 |
2.5V |
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(xxxx) =
(yy) = |
Module speed (MHz) and Cas Latency
266A: 266Mhz CL2
333B: 333Mhz CL2.5
400C: 400Mhz CL3
DRAM Manufacturer and Die Revision
P: Samsung
H: Micron
C: Hynix |
A: A-Die
B: B-Die
C: C-Die |
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(z) = |
Buffer / Register set (Only applies to Registered/Buffered modules)
I: Inphi
D: IDT/ICS
L: Intel |
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