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DRAM SDR
SDR
 

SDRAM – Synchronous Dynamic Random Access Memory can accept one command and transfer one word of data per clock cycle, typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits) but chips are generally assembled into 168-pin DIMM modules that read or write 64 (non-ECC) or 72 (ECC) bits at a time. For space constrained designs, 144-pin SODIMM modules are a smaller form-factor alternative. SDRAM 168-pin and 144-pin modules are now considered legacy product, which Wintec is committed to continue supporting based on availability of raw materials. From the original SDRAM, further generations of modules are now available, DDR1, DDR2 and DDR3 (which is becoming the mainstream technology in 2010), with DDR4 currently being designed and anticipated to be available in year 2012.

 
SDR - 168-Pin DIMM - Registered ECC
Standard Profile (1.0”) with Nominal Voltage (3.3V)
Density Part Number Rank DIMM
Config
Component
Config
Voltage
128MB WSDRE128X809-xxxx-yyz 1 Rank 16x72 16Mx8 3.3V
256MB WSDRE256X809-xxxx-yyz 1 Rank 32x72 32Mx8 3.3V
512MB WSDRE512X809-xxxx-yyz 1 Rank 64x72 64Mx8 3.3V
WSDRE512X818-xxxx-yyz 2 Rank 64x72 32Mx8 3.3V
1GB WSDRE01GX818-xxxx-yyz 2 Rank 128x72 64Mx8 3.3V
 
(xxxx) =




(yy) =
Module speed (MHz)
and Cas Latency
100A: 100Mhz CL2
133C: 133Mhz CL3

DRAM Manufacturer and Die Revision
P: Samsung
H: Micron
C: Hynix     
A: A-Die
B: B-Die
C: C-Die
(z) = Buffer / Register set
(Only applies to Registered/Buffered modules)
P: Pericom
S: Silego
T: TI
 
 
 
 
 
 
 
 
 
 
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